This invention relates generally to backplanes in computers and other electronic devices and more particularly to memory backplanes that use memory modules.
Many electronic devices, such as computers, use arrays of memory modules inserted into sockets along a backplane to store digital information. Two common types of memory modules are SIMMs (Single Inline Memory Modules) and DIMMs (Dual Inline Memory Modules). Memory modules tend to use less board space and are more compact than some memory-mounting arrangements. These modules also allow memory capacity to be increased by replacing modules or inserting additional modules.
Unfortunately, some ways of connecting signals to an array of memory modules can cause signal integrity problems. For example, if a xe2x80x9ccomb topologyxe2x80x9d is used as shown in FIG. 1, then the wavefront of the signal driven to the memory modules degrades at each junction. This causes the signal at the last memory modules to have signal characteristics similar to those shown in the shape shown in FIG. 2. The ripples and bumps shown on the rising and falling edges of the waveform in FIG. 2 are problematic. These non-ideal edges are particularly problematic for source synchronous systems, such as DDR (double data rate synchronous) DRAM. In a source synchronous system, the non-ideal edges can lead to false latching of signals. Furthermore, each module of the comb topology receives the driven signal with a different propagation delay. This has the effect of reducing timing budgets. Finally, each module of the comb topology has receives a different shaped signal and this makes analysis and verification of the electrical properties of the array of memory modules more difficult.
Accordingly, there is a need in the art for a memory module array design that helps optimize the signal characteristics of signals received by each module in the array and also helps optimize the cost of implementing the memory module array.
A preferred embodiment of the invention utilizes a hybrid topology that helps improve the signal characteristics of signals received by industry standard open stub memory modules or other types of modules. A memory or other module array according to the invention includes a lead-in transmission line from a driving source. The lead-in transmission line ends with a series impedance between the lead-in transmission line and a star node. The star node has a terminating impedance between it and a termination voltage. At least two branch transmission lines diverge from the star node. Modules connect to the branch transmission lines in a comb topology.